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CWE-1271: Missing Known Value on Reset for Registers Holding Security Settings

Weakness ID: 1271
Abstraction: Class
Structure: Simple
Status: Incomplete
Presentation Filter:
+ Description
The product's logic for state elements that implement security-critical functionality does not have a mechanism for being initialized to a known value on reset.
+ Extended Description

When a circuit is first brought out of reset, the state of storage elements will be unknown if not explicitly initialized by the logic. If registers holding security-critical state are not properly initialized before being used to control access to design assets or critical resources, there will be a timing window during which the device is in an insecure state and vulnerable to attack.

+ Relationships

The table(s) below shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

+ Relevant to the view "Research Concepts" (CWE-1000)
ChildOfClassClass - a weakness that is described in a very abstract fashion, typically independent of any specific language or technology. More specific than a Pillar Weakness, but more general than a Base Weakness. Class level weaknesses typically describe issues in terms of 1 or 2 of the following dimensions: behavior, property, and resource.665Improper Initialization
+ Relevant to the view "Hardware Design" (CWE-1194)
MemberOfCategoryCategory - a CWE entry that contains a set of other entries that share a common characteristic.1206Power, Clock, and Reset Concerns
+ Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

ImplementationThis weakness can be manifest during this phase if registers that hold security-critical state are not implemented to initialize to a secure value upon reset.
+ Applicable Platforms
The listings below show possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.


Class: Language-Independent (Undetermined Prevalence)

Operating Systems

Class: OS-Independent (Undetermined Prevalence)


Class: Architecture-Independent (Undetermined Prevalence)


Class: Technology-Independent (Undetermined Prevalence)

+ Common Consequences

The table below specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.

Access Control

Technical Impact: Varies by Context

The attacker may gain access to some resources if the state of the access control circuitry is not set to a known value on reset.
+ Demonstrative Examples

Example 1

Shown below is a positive clock edge triggered flip-flop used to implement a lock bit for the test and debug interface. When the circuit is first brought out of reset, the state of the storage element will be unknown until the enable and d-input signals update the stored value. In this example, an attacker can reset the device until the test and debug interface is unlocked and access the test interface until the lock signal is driven to a known state by the logic.

(bad code)
Example Language: Other 
always @(posedge clk) begin
if (en) lock_jtag <= d;

The flip-flop can be set to a known value (0 or 1) on reset, but requires that the logic explicitly update the output of the flip-flop if the reset signal is active.

(good code)
Example Language: Other 
always @(posedge clk) begin
if (~reset) lock_jtag <= 0;
else if (en) lock_jtag <= d;
+ Potential Mitigations

Phase: Implementation

Perform design checks to identify any uninitialized flip-flops in the design to ensure none are security-critical.

Phase: Architecture and Design

All registers holding security-critical state should be set to a secure value explicitly on reset or carefully designed to ensure that the inputs of the register update the contents to a secure value before any downstream logic is affected by the security state.
+ Notes


This entry is still under development and will continue to see updates and content improvements.
+ Content History
+ Submissions
Submission DateSubmitterOrganization
2020-05-15Nicole FernTortuga Logic
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Page Last Updated: June 25, 2020