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CWE-1272: Debug/Power State Transitions Leak Information

Weakness ID: 1272
Abstraction: Base
Structure: Simple
Status: Incomplete
Presentation Filter:
+ Description
Sensitive information may leak as a result of a debug or power state transition when information access restrictions change as a result of the transition.
+ Extended Description

A device or system frequently employs many power and sleep states during its normal operation (e.g., normal power, additional power, low power, hibernate, deep sleep, etc.). Similarly, depending on the supplied credentials, a device may be operating within a debug condition. For example, a hypothetical enumeration of debug levels may be:

  • Level 1 (fully open, all debug methods available)
  • Level 2 (partially open, some debug methods available), and
  • Level 3 (not open, minimal to no debug methods available).

Depending on various factors, state transitions can happen from one power or debug state to another. If there is information available in the current state and it is not properly removed before the next transistion state, there can be sensitive information leakage.

+ Relationships

The table(s) below shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

+ Relevant to the view "Research Concepts" (CWE-1000)
ChildOfPillarPillar - a weakness that is the most abstract type of weakness and represents a theme for all class/base/variant weaknesses related to it. A Pillar is different from a Category as a Pillar is still technically a type of weakness that describes a mistake, while a Category represents a common characteristic used to group related things.664Improper Control of a Resource Through its Lifetime
+ Relevant to the view "Hardware Design" (CWE-1194)
MemberOfCategoryCategory - a CWE entry that contains a set of other entries that share a common characteristic.1207Debug and Test Problems
+ Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

Architecture and Design
+ Applicable Platforms
The listings below show possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.


VHDL (Undetermined Prevalence)

Verilog (Undetermined Prevalence)

Class: Compiled (Undetermined Prevalence)

Operating Systems

Class: OS-Independent (Undetermined Prevalence)


Class: Architecture-Independent (Undetermined Prevalence)


Other (Undetermined Prevalence)

Class: Technology-Independent (Undetermined Prevalence)

+ Common Consequences

The table below specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.

Access Control

Technical Impact: Read Memory; Read Application Data

Depending on the information that is compromised, an attacker can use that information to unlock additional capabilities of the device and take advantage of hidden functionalities. This could compromise any security property, including the ones listed above.
+ Demonstrative Examples

Example 1

This example shows how an attacker can take advantage of an incorrect, power/debug-state transition.

(bad code)

Suppose a device is transitioning from state A to state B. During state A, it can read certain private keys from the hidden fuses that are only accessible in state A but not in B. It reads those keys, performs certain operations, and then transitions to state B where those private keys are no longer accessible.

However, during this transition, it does not scrub the memory. So, at this moment, even though the private keys are no longer accessible directly from the fuses in state B, they can be accessed indirectly by reading the memory, which contains the footprint of the private keys.

It is essential to consider not just the source of the secrets but, rather, perform a taint analysis of how far the secrets have traveled.

(good code)
For transition from state A to state B, do a taint analysis of where confidential information has propagated. Make sure all secrets from all such locations are removed during the transition.
+ Potential Mitigations

Phase: Architecture and Design

During state transitions, it is essential that the device also take appropriate action to scrub the secrets that are available in the current state but should not be available in the next state.
+ Content History
+ Submissions
Submission DateSubmitterOrganization
2020-05-31Parbati Kumar Manna, Hareesh Khattri, Arun KanuparthiIntel Corporation
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Page Last Updated: June 25, 2020