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CWE-1326: Missing Immutable Root of Trust in Hardware

Weakness ID: 1326
Abstraction: Base
Structure: Simple
Status: Draft
Presentation Filter:
+ Description
A missing immutable root of trust in the hardware results in the ability to bypass secure boot or execute untrusted or adversarial boot code.
+ Extended Description

A System-on-Chip (SoC) implements secure boot by verifying or authenticating signed boot code. The signing of the code is achieved by an entity that the SoC trusts. Before executing the boot code, the SoC verifies that the code or the public key with which the code has been signed has not been tampered with. The other data upon which the SoC depends are system-hardware settings in fuses such as whether “Secure Boot is enabled”. These data play a crucial role in establishing a Root of Trust (RoT) to execute secure-boot flows.

One of the many ways RoT is achieved is by storing the code and data in memory or fuses. This memory should be immutable, i.e., once the RoT is programmed/provisioned in memory, that memory should be locked and prevented from further programming or writes. If the memory contents (i.e., RoT) are mutable, then an adversary can modify the RoT to execute their choice of code, resulting in a compromised secure boot.

Note that, for components like ROM, secure patching/update features should be supported to allow authenticated and authorized updates in the field.

+ Relationships

The table(s) below shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

+ Relevant to the view "Research Concepts" (CWE-1000)
ChildOfPillarPillar - a weakness that is the most abstract type of weakness and represents a theme for all class/base/variant weaknesses related to it. A Pillar is different from a Category as a Pillar is still technically a type of weakness that describes a mistake, while a Category represents a common characteristic used to group related things.693Protection Mechanism Failure
+ Relevant to the view "Hardware Design" (CWE-1194)
MemberOfCategoryCategory - a CWE entry that contains a set of other entries that share a common characteristic.1196Security Flow Issues
+ Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

Architecture and Design
ImplementationSuch issues could be introduced during policy definition, hardware architecture, design, manufacturing, and/or provisioning and can be identified later during testing or system configuration phases.
+ Applicable Platforms
The listings below show possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.


Class: Language-Independent (Undetermined Prevalence)

Operating Systems

Class: OS-Independent (Undetermined Prevalence)


Class: Architecture-Independent (Undetermined Prevalence)


Security IP (Undetermined Prevalence)

Class: Technology-Independent (Undetermined Prevalence)

+ Common Consequences

The table below specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.


Technical Impact: Gain Privileges or Assume Identity; Execute Unauthorized Code or Commands; Modify Memory

+ Demonstrative Examples

Example 1

The RoT is stored in memory. This memory can be modified by an adversary. For example, if an SoC implements “Secure Boot” by storing the boot code in an off-chip/on-chip flash, the contents of the flash can be modified by using a flash programmer. Similarly, if the boot code is stored in ROM (Read-Only Memory) but the public key or the hash of the public key (used to enable “Secure Boot”) is stored in Flash or a memory that is susceptible to modifications or writes, the implementation is vulnerable.

In general, if the boot code, key materials and data that enable “Secure Boot” are all mutable, the implmentation is vulnerable.

Good architecture defines RoT as immutable in hardware. One of the best ways to achieve immutability is to store boot code, public key or hash of the public key and other relevant data in Read-Only Memory (ROM) or One-Time Programmable (OTP) memory that prevents further programming or writes.

+ Potential Mitigations

Phase: Architecture and Design

When architecting the system, the RoT should be designated for storage in a memory that does not allow further programming/writes.

Phase: Implementation

During implementation and test, the RoT memory location should be demonstrated to not allow further programming/writes.
+ Detection Methods

Automated Dynamic Analysis

Automated testing can verify that RoT components are immutable.

Effectiveness: High

Architecture or Design Review

Root of trust elements and memory should be part of architecture and design reviews.

Effectiveness: High

+ References
[REF-1152] Trusted Computing Group. "TCG Roots of Trust Specification". 2018-07. <>.
[REF-1153] GlobalPlatform Security Task Force. "Root of Trust Definitions and Requirements". 2017-03. <>.
+ Content History
+ Submissions
Submission DateSubmitterOrganization
2020-04-25Arun Kanuparthi, Hareesh Khattri, Parbati Kumar MannaIntel Corporation
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Page Last Updated: December 10, 2020