CWE - CWE-1324: Sensitive Information Accessible by Physical Probing of JTAG Interface (4.8)

Weakness ID: 1324

Abstraction: Base
Structure: Simple

Presentation Filter:

Description

Sensitive information in clear text on the JTAG interface may be examined by an eavesdropper, e.g. by placing a probe device on the interface such as a logic analyzer, or a corresponding software technique.

Extended Description

On a debug configuration with a remote host, unbeknownst to the host/user, an attacker with physical access to a target system places a probing device on the debug interface or software related to the JTAG port e.g. device driver. While the authorized host/user performs sensitive operations to the target system, the attacker uses the probe to collect the JTAG traffic.

Relationships

This table shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

Relevant to the view "Research Concepts" (CWE-1000)

Nature	Type	ID	Name
ChildOf	Class - a weakness that is described in a very abstract fashion, typically independent of any specific language or technology. More specific than a Pillar Weakness, but more general than a Base Weakness. Class level weaknesses typically describe issues in terms of 1 or 2 of the following dimensions: behavior, property, and resource.	300	Channel Accessible by Non-Endpoint

Relevant to the view "Hardware Design" (CWE-1194)

Nature	Type	ID	Name
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1207	Debug and Test Problems

Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

Phase	Note
Architecture and Design	May be introduced when design does not plan for an attacker having physical access while legitimate user is remotely operating device
Implementation

Applicable Platforms

This listing shows possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.

Languages

Class: Language-Independent (Undetermined Prevalence)

Operating Systems

Class: OS-Independent (Undetermined Prevalence)

Architectures

Class: Architecture-Independent (Undetermined Prevalence)

Technologies

Test/Debug Hardware (Undetermined Prevalence)

Class: System on Chip (Undetermined Prevalence)

Common Consequences

This table specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.

Scope	Impact	Likelihood
Confidentiality	Technical Impact: Read Memory; Read Files or Directories; Read Application Data	High

Demonstrative Examples

Example 1

A TAP accessible register is read/written by a JTAG based tool, for internal tool use for an authorized user. The JTAG based tool does not provide access to this data to an unauthorized user of the tool. However, the user can connect a probing device and collect the values directly from the JTAG interface, if no additional protections are employed.

Potential Mitigations

Phase: Manufacturing

Disable permanently the JTAG interface before releasing the system to untrusted users.

Effectiveness: High

Phase: Architecture and Design

Encrypt all information (traffic) on the JTAG interface using an approved algorithm (such as recommended by NIST). Encrypt the path from inside the chip to the trusted user application.

Effectiveness: High

Phase: Implementation

Block access to secret data from JTAG.

Effectiveness: High

Related Attack Patterns

CAPEC-ID	Attack Pattern Name
CAPEC-150	Collect Data from Common Resource Locations
CAPEC-167	White Box Reverse Engineering
CAPEC-545	Pull Data from System Resources

Content History

Submissions
Submission Date	Submitter	Organization
2020-10-01	Accellera IP Security Assurance (IPSA) Working Group	Accellera Systems Initiative
2020-10-01
Modifications
Modification Date	Modifier	Organization
2021-10-28	CWE Content Team	MITRE
2021-10-28	updated Potential_Mitigations
2022-04-28	CWE Content Team	MITRE
2022-04-28	updated Applicable_Platforms
2022-06-28	CWE Content Team	MITRE
2022-06-28	updated Applicable_Platforms


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Common Weakness Enumeration

CWE-1324: Sensitive Information Accessible by Physical Probing of JTAG Interface